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3.3 v 3.2 gb/s limiting amplifier preliminary technical data adn2891 rev. pr a. in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features sfp reference design availabl e input sensitivit y: 4 m v p-p 80 ps rise/fal l ti mes cml outputs: 7 00 mv p-p diffe rential programmable los detector: 3mv to 40 mv rx signal stren g th indicator (rssi): sff-8472 compliant aver age power measurement single-supply operation: 3.3 v low power dissipation: 145 mw avail a ble in sp ace-saving 3 m m 3 mm 16 -le a d lfcsp extended tem perature rang e: -40 o c t o 9 5 o c applic ati o ns sfp/sff/gbic optical transceivers oc-3/12/48, gb e, fibre chann e l receivers 10gbase-lx4 t r ansceivers wdm transponders general description the adn2891 l i mi t i n g am p l if ier w o rks as a da t a q u an t i zer o p t i m i ze d fo r sonet , gigab i t e t h e r n et (gbe), a nd f i b r e cha nne l o p t i cal r e cei v ers in t h e ra n g e o f 155m p b s an d u p t o 3.2gb p s . i t acc e p t s in p u t leve ls o f u p t o 2.0 v p-p dif f er en t i al wi t h 4 m v p-p dif f er en t i al i n p u t s e n s i t ivi t y an d o u t p u t s c u r r en t m o d e l o gi c (c ml ) v o l t a g e s w i th co n t r o ll ed e d g e s p eed s . . the adn2891 m e as ur es a v er ag e r e cei v ed p o wer bas e d o n a d i r e ct m e as ur em en t o f t h e ph o t od iod e curr e n t w i th bet t e r tha n 1 db o f acc u rac y o v er t h e e n t i r e in p u t ra n g e o f t h e r e ceiv er . thi s e l im in a t es t h e ne e d fo r ext e r n a l rss i de t e c t io n cir c ui t r y in s f f - 8472 co m p lian t o p tical tran s c eiv e rs. a d di t i o n a l fe a t ur es in cl u d es a p r og ra mma b l e los s -o f-sig n al (los) dete c t and o u tp u t s q uelch. the adn2891 l i mi t i n g am p l if ier o p era t es f r o m a sin g le 3.3 v su p p ly , has l o w p o we r diss i p a t i o n, and is a v ai l a bl e in a 3 m m 3 mm 16-le ad le ad f r a m e c h i p s c ale p a c k a g e (lfcs p ). func tio n a l block di agram pd _ v c c p d _ c a t hode a d n2 880 c az 1 c az 2 0. 01 f v re f +v ad u c 7 0 2 0 10 k ? f i gur e 1 . adn2 891 t y pi c a l a p pl ic at i o n circuit
adn2891 preliminary technical data rev. pra | page 2 of 12 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 8 limamp ....................................................................................... 8 loss of signal (los) detector .....................................................8 received signal strength indicator (rssi) ................................8 squelch mode ................................................................................8 applications information .................................................................9 pcb design guidelines ................................................................9 outline dimensions ....................................................................... 11 ordering guide .......................................................................... 11 revision history revision pra: initial version
preliminary technical data adn2891 rev. pra | page 3 of 12 specifications table 1. test conditions: vcc = 3.0v to 3.6v, vee = 0 v, t a = -40 o c to 95 o c , unless otherwise noted. parameter min typ max unit test conditions/comments quantizer dc characteristics input voltage range 1.8 2.8 v p-p @ pin or nin, dc-coupled input common mode 2.1 2.7 v dc-coupled peak-to-peak differential input range 2.0 v p-p pin ? nin, ac-coupled input sensitivity 4 3 mv p-p pin ? nin, ber 1 10 ?10 input offset voltage 100 v input rms noise 205 v rms input resistance 50 ? single-ended input capacitance 0.65 pf quantizer ac characteristics input data rate 155 3200 mb/s small signal gain 51 db differential s11 ?10 db differential, f < 3.2 ghz s22 ?10 db differential, f < 3.2 ghz random jitter 2.4 5 ps rms input > 10 mv p-p, oc-48, prbs 2 23 ? 1 deterministic jitter 13.7 19 ps p-p input > 10 mv p-p, oc-48, prbs 2 23 ? 1 low frequency cutoff 30 khz caz = open 1.0 khz caz = 0.0 1 f power supply rejection 45 db 100 khz < f < 10 mhz loss of signal detector (los) los assert level tbd 2.0 tbd mv p-p r thradj = 1m? tbd 40 tbd mv p-p r thradj = 500 ? hysteresis 3.0 tbd db oc-3, prbs 2 23 ? 1, r thradj = 500 ? tbd 3.0 db oc-3, prbs 2 23 ? 1, r thradj = 1m? 4.5 tbd db oc-48, prbs 2 23 ? 1, r thradj = 500 ? tbd 4.5 db oc-48, prbs 2 23 ? 1, r thradj = 1m ? los assert time 600 ns dc-coupled los de-assert time 100 ns dc-coupled rssi input current range 5 1000 a rssi output accuracy 15% i in 20 a 10% i in > 20 a gain 1.0 ma/ma i rssi /i pd offset 50 na compliance voltage v cc ? 0.9 v cc ? 0.3 v @ pd_cathode power supplies v cc 3.0 3.3 3.6 v i cc 44 60 ma operating temperature range ?40 +25 +95 c t min to t max cml output characteristics output impedance 50 ? single-ended output voltage swing 600 700 800 v p-p differential output rise and fall time 80 100 ps 20% to 80% logic inputs (squelch) v ih , input high voltage 2.0 v v il , input low voltage 0.8 v input current ?100 na i inh , v in = 2.4 v 100 na i inl , v in = 0.4 v
adn2891 preliminary technical data rev. pra | page 4 of 12 parameter min typ max unit test conditions/comments logic outputs (los) v oh , output high voltage 2.4 v open drain output, 4.7 k? ? 10 k? pull-up resistor to v cc v ol , output low voltage 0.4 v open drain output, 4.7 k? ? 10 k? pull-up resistor to v cc
preliminary technical data adn2891 r e v. pr a | pa g e 5 of 12 absolute maximum ratings table 2. p a r a m e t e r r a t i n g supply voltage 4.2 v m i nimum input voltage ( a ll inp uts) vee ? 0.4 v m a ximum input voltage ( a ll inputs) vcc + 0.4 v storage temperature ?65c to +155c operating temperature range ?40c to +95c lead temperature range (soldering 10 s) 300c junction tempe r ature 125c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly a n d f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i ndic a t e d i n t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . thermal resistance ja is sp e c if ie d fo r 4-la yer pcb wi t h exp o s e d p a dd le s o lder e d to g n d . table 3. package type ja unit 16-lead 3 mm 3 mm lfcsp 28 c/w esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adn2891 preliminary technical data r e v. pr a | pa g e 6 of 12 pin conf iguration and fu nction descriptions dr v c c ou t p ou t n dr v e e av c c pi n ni n av e e p d _ c a t h o d e p d _ v c c r s s i _ o u t s q u e l c h t h r a d j c a z 1 c a z 2 l o s 1 2 3 4 5 6 7 8 12 11 10 9 1 6 1 5 1 4 1 3 ad n 2 8 9 1 to p v i e w ( n o t t o s c al e) f i gure 2. pin config ur ation note: there is an exposed pad on t h e bottom o f the package that mu st be conne cted to the gnd p l ane with f illed v i as. ta ble 4. pi n f u nct i on des c ri pt i o ns pin no. mnemonic i/o description 1 a v c c p o w e r a n a l o g p o w e r 2 pin input differential data input 3 nin input differential data input 4 a v e e p o w e r a n a l o g g r o u n d 5 t h radj input los t h reshold ad just resistor 6 caz1 offset correctio n loop cap a cito r 7 caz2 offset correctio n loop cap a cito r 8 los output los detector output 9 d r v e e p o w e r o u t p u t b u f f e r g r o u n d 1 0 o u t n o u t p u t differe ntial data output 1 1 o u t p o u t p u t differe ntial data output 1 2 d r v c c p o w e r o u t p u t b u f f e r p o w e r 1 3 s q u e l c h i n p u t d i s a b l e o u t p u t s 14 rssi_out output average current output 15 pd_vcc power power input for rssi measurement 16 pd_cathode output photodiode bias voltage exposed pad pad power connect to ground
preliminary technical data adn2891 r e v. pr a | pa g e 7 of 12 typical perf orm ance cha r acte ristics 04509-0-002 0 0 0.1 0.2 0.3 0.4 0.5 rssi_in (ma) 0.6 0.7 0.8 0.9 1.0 rs s i _ o ut (ma) 0.88 0.96 0.80 0.72 0.64 0.56 0.48 0.40 0.32 0.24 0.16 0.08 f i g u re 3. r ssi o u t p ut v s . a v er ag e pin p h ot odi o de cu rren t l o s tr i p p o i n t -v s - r t h r a d j 0 10 20 30 40 50 10 100 1000 10000 100000 oh m s mv f i gur e 4 . l o s t r i p p o i n t vs . thr e sho l d a d just resi st o r 04509-0-010 0 10 20 30 40 50 60 100k 1m supply-noise frequency (hz) 10m s u p p l y - nois e re j e ction (db) 70 f i g u re 5. t y pic a l p s r r v s . sup p ly-nois e f r eq uenc y 04509-0-020 vertical scale: 100mv/div f i g u re 6. eye d i ag r a m at 3.2 gb/s 04509-0-021 vertical scale: 100mv/div f i g u re 7. eye d i ag r a m at 2.4 8 8 gb/s
adn2891 preliminary technical data rev. pra | page 8 of 12 theory of operation limamp input buffer the adn2891 limiting amplifier has differential inputs (pin/nin), with an internal 50 ? termination. the amplifier input supports dc- or ac-coupled to tias. in real applications, the rosa (receive optical sub-assembly) is typically ac- coupled to the amplifier inputs because if dc-coupled, tia output offset degrades receiver performance. the adn2891 limiting amplifier is a high gain device. it is susceptible to dc offsets in the signal path. the pulse-width distortion present in a 50% duty cycle nrz data or distortion generated from tia appears as a dc offset to the inputs. an internal offset correction loop requires that a capacitor be connected between the caz1 and caz2 pins. for gbe and fc applications, no external capacitor is necessary, but for sonet applications, a 0.01 f capacitor provides the data path a lower 3db frequency cutoff of 1 khz. cml output buffer the adn2891 provides cml outputs, outp/outn. the outputs are internally terminated with 50 ? to vcc. the outputs can be kept at a static voltage by driving the squelch pin to a logic high. the squelch pin can be driven directly by the los pin, which automatically disables the amplifer outputs in situations when the input signal level drops below the programmed los threshold. loss of signal (los) detector the receiver front-end los detector circuit indicates when the input signal level has fallen below the user-adjustable threshold. the threshold level can be set to anywhere from 2mvpp to 40mvpp, typically, and is set by a resistor connected between the thradj pin and v ee . see figure 4 for a plot of los threshold -vs- thradj. the adn2891 los circuit has a trip point down to <3.0 mv with >3 db electrical hysteresis to prevent chatter at the los output. the los output is an open- collector output that must be pulled up externally with a 4.7 k? to 10 k? resistor. received signal strength indicator (rssi) the adn2891 has an on-chip rssi circuit. with a photodiode biased directly by the adn2891, a very accurate, on-chip, average power measurement is available via the rssi circuit by monitoring the current supplied to the photodiode. the output of the rssi is a current that is directly proportional to the average amount of pin photodiode current. placing a resistor between the rssi_out pin and gnd converts the current to a gnd referenced voltage. this function eliminates the need for external rssi circuitry in sff-8472 compliant optical receivers. squelch mode driving the squelch input to a logic high disables the limiting amplifier outputs. the squelch input can be connected to the los output to keep the limiting amplifier outputs at a static voltage level anytime the input level to the limiting amplifier drops below the programmed los threshold.
preliminary technical data adn2891 r e v. pr a | pa g e 9 of 12 appli c ations inf ormati o n pcb desig n guideline s g e n e r i c rf pc b desig n te chni q u e a p plies w i t h sp e c ia l co n s idera t io n i m ple m en t e d fo r t h e op t i m a l p e r f o r ma n c e . out p ut buf f er pow er su pply an d g r o u nd p l anes pin 9 an d 12 a r e t h e p o w e r sup p ly a n d g r o u n d pin s to p r o v id e c u r r en t t o dif f er en t i al o u tp and o u tn pin s . t o r e d u ce an y p o s s i b le s e r i al ind u c t an ce , p i n 9, which is t h e g r o u n d r e t u r n o f t h e ou t p u t b u f f er , s h o u l d co nn e c t t o g r o u nd dir e c t l y . i f t h e g r o u n d plan e is a n in t e r n al plane a nd co nn ec t i o n s t o t h e g r o u n d plan e a r e v i as, m u l t i p le v i as i n p a ra l l el to t h e g r o u n d ca n r e d u ce t h e s e r i es ind u c t anc e .. s i mi la rl y , t o r e d u ce the p o s s i b le s e r i es in d u c t ance , p i n 12, w h ich s u p p lie s p o w e r t o t h e hi g h -sp e e d dif f er en t i al ou t p / o u t n output bu f f e r , s h ou l d c o n n e c t t o p o we r pl a n e dir e c t ly . i f t h e p o w e r plan e is an in t e r n a l plan e and co n n e c t i o n s t o t h e p o w e r plan e a r e v i as, m u lt i p le v i as in p a r a l l el can r e d u c e th e s e r i es ind u c t a n c e , es p e cial l y o n p i n 12. p l eas e r e f e r t o th e s c h e ma tic in f i gur e 8 f o r th e co nn ec t i o n r e commenda t ion. the ex p o s e d p a d sh o u ld b e con n e c te d to t h e g n d plane usin g f i ll ed vi a s s o t h a t s o lder do es n o t le ak t h r o ug h t h e v i as d u r i n g r e f l o w . u s i n g f i ll ed vi a s i n pa ral l e l un d e r t h e pac k a g e gr ea tl y r e d u ce t h e t h er mal r e sis t a n ce and enhan c es t h e r e l i a b i l i t y o f t h e co nn e c t i vi ty o f t h e ex p o s e d p a d to t h e g n d plan e d u r i n g re f l o w . t o r e d u ce p o w e r n o is e , a 10 f e l ec tr ol ytic dec o u p lin g c a p a ci to r bet w een v c c a n d v ee i s a t th e loca ti o n w h e r e th e 3. 3 v s u p p l y en t e rs t h e pcb . the o t h e r 0.1 f a n d 1 nf ceramic c h i p de co u p ling ca p a ci t o rs sh o u ld b e as clos e as p o ssi b l e t o t h e ad n2891 v cc a nd vee p i ns to r e d u ce a n y p o s s i b le c u r r en t re tu r n l o op . 04509-0-007 connect exposed pad to gnd avcc 1 thradj 5 caz1 6 caz2 7 los 8 p d _ cathode 16 pd _vc c 15 r ssi_ou t 14 squ e lc h 13 pin 2 nin 3 avee 4 drvcc 12 outn 10 drvee 9 outp c4 c3 11 c2 c1 to host board c7 c8 vcc c5 c6 vcc c11 c12 r2 200 ? vcc r3 4.7k ? to 10k ? on host board vcc adn2880 0.1 f vcc c9 rssi measurement to adc r1 c10 c1?c4, c11: 0.01 f x5r/x7r dielectric, 0201 case c5, c7, c9, c10, c12: 0.1 f x5r/x7r dielectric, 0402 case c6, c8: 1nf x5r/x7r dielectric, 0201 case f i g u re 8. t y pic a l a dn2 89 1 a p p l i c at i o ns circuit
adn2891 preliminary technical data r e v. pr a | pa g e 10 o f 12 pcb layout f i gur e 9 sh o w s a r e co mm en de d pc bo a r d la yo u t . th e 50 ? t r a n smis sio n l i nes a r e t h e t r aces t o b r in g t h e hig h f r e q uen c y in p u t an d o u t p ut sig n a l s: pin , nin, ou tp and ou tn to t h e s m a co nn ect o rs wi th m i ni m u m r e f l ecti o n s. t o a v o i d a si gn al s k e w b e t w e e n t h e dif f er en t i al t r aces, e a ch dif f er en t i al p i n/ ni n p a ir a nd t h e dif f er en t i al o u tp / o utn p a ir sh ou ld ha v e t h eir ma t c h e d t r ace l e n g t h t o t h e s m a co nn e c t o rs. c 1 , c2, c3, an d c4 a r e ac-co u p l in g c a p a ci t o rs in s e r i es wi th t h e hig h s p ee d i/o . t o mini mi ze t h e p o ssi b l e mism a t ch , t h e a c cou p lin g c a p a ci to r p a d sh o u ld be t h e s a me wid t h as tha t o f t h e 50 ? tra n smis sio n line . the tra n s m is sio n l i n e s sho u ld be in s a me wid t h, o n s a m e sig n a l pla t e, n o la yer cha n ges, r u n f r o m t h e hig h sp e e d p a ds dir e c t ly to s m a co nn e c to rs. f o r su p p ly de co u p l i n g , t h e 1 nf deco u p ling ca p a ci t o r sh o u ld be p l aced on t h e s a m e l a yer as th e ad n2891 as c l os e as p o s s i b l e to th e v c c p i n. the 0.1 f ca p a ci t o r ca n be p l aced on t h e b o t t om o f the pc b dir e c t l y un der n e a t h t h e 1 nf deco u p lin g ca p a ci t o r . al l hig h sp ee d cml output s h a v e on ch ip , 5 0 ? re s i st or s te r m i n ate d b e t w e e n t h e o u t p ut p i n an d v c c. t h e hi g h sp e e d in p u ts, pi n an d nin , a l s o h a ve t h e i n te r n a l ly 5 0 ? te r m i n a t e d to a n i n te r n a l re fe re nc e vol t age. a s wi t h an y hi g h sp e e d m i xe d- sig n a l desig n , m a k e sur e to k e ep all h i g h s p ee d di gi tal traces a w a y f r o m sen s i t i v e a n alog n o d e s. soldering gui d elines for chi p scale package the lan d s on t h e 16 lfcs p a r e r e c t a n gu la r . the p r in t e d cir c u i t b o a r d p a d fo r t h es e sh o u ld b e 0.1 mm lo n g er t h a n t h e p a cka g e lan d len g th and 0.05 mm wider tha n t h e p a ckag e lan d wid t h. the land sh o u l d b e cen t er e d on t h e p a d . this en s u r e s t h a t t h e s o lder jo in t si ze is maximize d . the b o t t o m o f t h e chi p s c ale pa c k a g e h a s a ce n t r a l e x posed pa d . th e pad o n th e p r in t e d cir c ui t bo a r d sho u ld be a t le as t as la rg e as this e x p o s e d p a d . the us er m u s t co nne c t t h e exp o s e d p a d t o vee usin g f i l l e d v i as s o t h a t s o lder do es n o t le ak t h r o ug h t h e v i as d u r i ng r e f l o w . this en sur e s a s o li d co nn e c t i o n f r o m t h e ex p o s e d p a d to vee. 04509-0-008 1 vias to gnd exposed pad pin nin via to c12, r2 on bottom c11 via to bottom double-via to gnd to reduce inductance c3 c8 c4 c1 c6 c2 outp double-vias to reduce inductance to supply and gnd r1, c9, c10 on bottom to rosa place c7 on bottom of board underneath c8 outn place c5 on bottom of board underneath c6 4mm f i gure 9. recommended adn 2 891 pc b lay o ut ( t o p vie w )
preliminary technical data adn2891 r e v. pr a | pa g e 11 o f 12 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq to p v i e w 12 max 0.80 max 0.65 typ sea ting plane pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq 1.65 1.50 sq * 1.35 bot t om vi e w 16 5 13 8 9 12 4 * compliant t o jedec st and ards mo-220-veed-2 except for exposed p ad dimension f i gure 10. 1 6 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] 3 mm 3 m m b o d y (c p - 1 6 - 3 ) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package desc ri p t i o n p a c k a g e o p t i o n b r a n d i n g adn2891acp C40c to +95c 16-lfcsp cp-16-3 f02 adn2891acp- r l C40c to +95c 16-lfcsp cp-16-3 f02 adn2891acp- r l7 C40c to +95c 16-lfcsp cp-16-3 f02
adn2891 preliminary technical data r e v. pr a | pa g e 12 o f 12 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners .

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